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this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sales o f the product. 1/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology features general description block diagram ? horizontal sync input may be up to 120 khz. ? acceptable wide-range pixel clock up to 96mhz from xin pin. ? full-screen display consists of 15 (rows) by 30 (col- umns) characters. ? 12 x 18 dot matrix per character. ? total of 256 characters and graphic fonts including 248 mask rom fonts and 8 programmable ram fonts. ? 8 color selection maximum per display character. ? double character height and/or width control. ? programmable positioning for display screen cen- ter. ? bordering, shadowing and blinking effect. ? programmable vertical character height (18 to 71 lines) control. ? row to row spacing register to manipulate the con- stant display height. ? 4 programmable background windows with multi- level operation. ? software clears for display frame. ? half tone and fast blanking output. ? 8-channel/8-bit pwm d/a converter output. ? compatible with spi bus or i 2 c interface with address 7ah (slave address is mask option). ? 16 or 24-pin pdip/sop package. on-screen-display for lcd monitor MTV118 is designed for lcd monitor appli- cations to display the built-in characters or fonts onto an lcd monitor screen. the display oper- ates by transferring data and control information from the micro controller to the ram through a serial data interface. it can execute full screen displays automatically and specific functions such as character bordering, shadowing, blinking, dou- ble height and width, font by font color control, frame positioning, frame size control by character height and windowing effect. moreover, MTV118 also provides 8 pwm dac channels with 8-bit resolution and a pwm clock output for external digital-to-analog control. serial data interface address bus administrator vertical display control display & row control registers color encoder windows & frame control wr wg wb fbkgc blank lumar lumag lumab blink vclkx data vertd hord ch 8 8 7 bsen shadow osdenb hsp vsp horizontal display control clock generator 8 data lpn cws vclks 5 data cws chs 8 lumar lumag lumab blink craddr 8 luma border arwdb hdren vclkx hord 8 ch chs vertd 7 8 lpn nrow vdren 5 rcaddr daddr fontaddr winaddr pwmaddr 5 9 9 5 5 arwdb hdren vdren nrow data row, col ack 8 9 character rom user font ram luminance & bordger generator vdd vss vdda vssa rout gout bout fbkg htone hflb nc xin vflb ssb sck sda vsp hsp pwm d/a converter pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 8 data 8 power on reset prb
2/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 1.0 pin connection 2.0 pin descriptions name i/o pin # descriptions n16 n24 vss - 1 1 ground. this ground pin is used for internal circuitry. xin i 2 2 pixel clock input. this is a clock input pin. MTV118 is driven by an external pixel clock source for all the logics inside. the fre- quency of xin must be the integral time of pin hflb. nc i 3 3 no connection. vdd - 4 4 power supply. positive 5 v dc supply for internal circuitry. a 0.1uf decoupling capacitor should be connected across vdd and vss. hflb i 5 5 horizontal input. this pin is used to input the horizontal synchro- nizing signal. it is a leading edge trigger and has an internal pull- up resistor. ssb i 6 6 serial interface enabler. it is used to enable the serial data and is also used to select the operation of i 2 c or spi bus. if this pin is left floating, i 2 c bus is enabled, otherwise the spi bus is enabled. sda i 7 7 serial data input. the external data transfers through this pin to internal display registers and control registers. it has an internal pull-up resistor. sck i 8 8 serial clock input. the clock-input pin is used to synchronize the data transfer. it has an internal pull-up resistor. pwm0 o - 9 open-drain pwm d/a converter 0. the output pulse width is programmable by the register of row 15, column 19. pwm1 o - 10 open-drain pwm d/a converter 1. the output pulse width is programmable by the register of row 15, column 20. pwm2 o - 11 open-drain pwm d/a converter 2. the output pulse width is programmable by the register of row 15, column 21. vss xin nc vdd hflb ssb sda sck vss rout gout bout fbkg htone/pwmck vflb vdd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MTV118 vss xin nc vdd hflb ssb sda sck pwm0 pwm1 pwm2 pwm3 vss rout gout bout fbkg htone/pwmck vflb vdd pwm7 pwm6 pwm5 pwm4 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 MTV118n24
3/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 3.0 functional descriptions 3.1 serial data interface the serial data interface receives data transmitted from an external controller. there are 2 types of bus which can be accessed through the serial data interface: spi bus and i 2 c bus. 3.1.1 spi bus when the ssb pin is pulled to a high or low level, the spi bus operation is selected. a valid trans- mission should start from pulling ssb to low level, enabling the MTV118 receiving mode and retaining the low level until the last cycle for a complete data packet transfer. the protocol is shown in figure1 on page4. there are 3 transmission formats as shown below: format (a) r - c - d ? r - c - d ? r - c - d format (b) r - c - d ? c - d ? c - d ? c - d format (c) r - c - d ? d ? d ? d ? d ? d r=row address, c=column address, d=display data pwm3 o - 12 open-drain pwm d/a converter 3. the output pulse width is programmable by the register of row 15, column 22. pwm4 o - 13 open-drain pwm d/a converter 4. the output pulse width is programmable by the register of row 15, column 23. pwm5 o - 14 open-drain pwm d/a converter 5. the output pulse width is programmable by the register of row 15, column 24. pwm6 o - 15 open-drain pwm d/a converter 6. the output pulse width is programmable by the register of row 15, column 25. pwm7 o - 16 open-drain pwm d/a converter 7. the output pulse width is programmable by the register of row 15, column 26. vdd - 9 17 power supply. positive 5 v dc supply for internal circuitry and a 0.1uf decoupling capacitor should be connected across vdd and vss. vflb i 10 18 vertical input. this pin is used to input the vertical synchronizing signal. it is triggered by lead and has an internal pull-up resistor. htone / pwmck o 11 19 half tone output / pwm clock output. this is a multiplexed pin selected by the pwmck bit. this pin can be a pwm clock or used to attenuate r, g, b gain of vga for the transparent windowing effect. fbkg o 12 20 fast blanking output. it is used to cut off external r, g, b sig- nals of vga while this chip is displaying characters or windows. bout o 13 21 blue color output. this is a blue color video signal output. gout o 14 22 green color output. this is a green color video signal output. rout o 15 23 red color output. this is a red color video signal output. vss - 16 24 ground. this ground pin is used for internal circuitry. name i/o pin # descriptions n16 n24
4/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 3.1.2 i 2 c bus i 2 c bus operation is only selected when the ssb pin is left floating. a valid transmission should begin from writing the slave address 7ah, which is mask option, to MTV118. the protocol is shown in figure 2 on page 4.. there are 3 transmission formats as shown below: format (a) s - r - c - d ? r - c - d ? r - c - d format (b) s - r - c - d ? c - d ? c - d ? c - d format (c) s - r - c - d ? d ? d ? d ? d ? d s=slave address, r=row address, c=column address, d=display data each arbitrary length of data packet consists of 3 portions: row address (r), column address (c) and display data (d). format (a) is suitable for updating small amounts of data which will be allocated with different row and column addresses. format (b) is recommended for updating data that has the same row address but a different column address. massive data updating or full screen data changes should be done in format (c) to increase transmission efficiency. the row and column addresses will be incre- mented automatically when format (c) is applied. furthermore, the undefined locations in display or font ram should be filled with dummy data. there are 3 types of data which should be accessed through the serial data interface: address bytes of display registers, attribute bytes of display registers and user font ram data. the protocol is the same for all except bits 5 and 6 of the row addresses. the msb(b7) is used to distinguish row and column addresses when transferring data from an external controller. bit 6 of the row address is used to distin- guish display registers and user font ram data and bit6 of the column address is used to differentiate the column address for formats (a), (b) and (c), respectively. bit 5 of the row address for display regis- ters is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to "1". the configuration of transmission formats is shown in table1 on page5. ms b lsb ssb sck sda first byte last byte figure 1. data transmission protocol (spi) figure 2. data transmission protocol (i 2 c) sck sda first byte ?@?@?@?@ ?@ start ack second byte last byte ack stop b7 b6 b0 b7 b0
5/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology the data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). the alternation between transmission for- mats is configured as the state diagram shown in figure3 on page5. 3.2 address bus administrator the administrator manages bus address arbitration of internal registers or user font ram during exter- nal data write-in. the external data write through serial data interface to registers must be synchronized by internal display timing. in addition, the administrator also provides automatic incrementation to the address bus when external writing occurs using format (c). 3.3 vertical display control the vertical display control can generate different vertical display sizes for most display standards in current monitors. the vertical display size is calculated with the information of a double character height bit(chs) and a vertical display height control register(ch6-ch0).the algorithms of a repeating charac- ter line display are shown in tables 2 and 3. the programmable vertical size range is 270 lines to max- imum 2130 lines. table 1. configuration of transmission formats address b7 b6 b5 b4 b3 b2 b1 b0 format address bytes of display reg. row 1 0 0 x r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b column c 0 1 x c4 c3 c2 c1 c0 c attribute bytes of display reg. row 1 0 1 x r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b column c 0 1 x c4 c3 c2 c1 c0 c user fonts ram row 1 1 x x x r2 r1 r0 a,b,c column ab 0 0 c5 c4 c3 c2 c1 c0 a,b column c 0 1 c5 c4 c3 c2 c1 c0 c initiate row col c col ab da c da ab 1, x 0, 1 0, 0 x, x x, x 0, 1 1, x 1, x format (a) format (b) format (c) x, x 0, x input = b7, b6 0, 0 figure 3. transmission state diagram
6/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology the vertical display center for a full-screen display may be figured out according to the information of the vertical starting position register (vertd) and vflb input. the vertical delay starting from the lead- ing edge of vflb is calculated using the following equation: vertical delay time = ( vertd * 4 + 1 ) * h where h = 1 horizontal line display time note: ?v? means the nth line in the character would be repeated once, while ?-? means the nth line in the character would not be repeated. 3.4 horizontal display control the horizontal display control is used to generate control timing for a horizontal display based on dou- ble character width bit (cws), horizontal positioning register (hord) and hflb input. a horizontal dis- play line includes 360 dots for 30 display characters and the remaining dots for a blank region. the horizontal delay starting from the hflb leading edge is calculated using the following equation: horizontal delay time = ( hord * 6 + 49) * p where p = 1 xin pixel display time 3.5 display & row control registers the internal ram contains display and row control registers. the display registers have 450 locations which are allocated between row 0/column 0 and row 14/column 29 as shown in figure 4. each display register has its corresponding character address on the address byte, and 1 blink bit and its corre- sponding color bits on attribute bytes. the row control register is allocated at column 30 for row 0 to row 14; it is used to set character size for each respective row. if the double width character (cws) is cho- table 2. repeat line weight of character ch6-ch0 repeat line weight ch6,ch5=11 +18*3 ch6,ch5=10 +18*2 ch6,ch5=0x +18 ch4=1 +16 ch3=1 +8 ch2=1 +4 ch1=1 +2 ch0=1 +1 table 3. repeat line number of character repeater line weight repeat line # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 - - - - - - - - v - - - - - - - - - +2 - - - - v - - - - - - - v - - - - - +4 - - v - - - v - - - v - - - v - - - +8 - v - v - v - v - v - v - v - v - - +16 - v v v v v v v v v v v v v v v v - +17 v v v v v v v v v v v v v v v v v - +18 v v v v v v v v v v v v v v v v v v
7/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology sen, only even column characters may be displayed on-screen and the odd column characters will be hidden. figure 4. memory map 3.5.1 register descriptions 1. (i) display register, (row 0 - 14, column 0 - 29) address byte craddr - defines rom character and user-programmable fonts address. (a) 0 ~ 247 t 248 built-in characters and graphic symbols (b) 248 ~ 255 t 8 user-programmable fonts attribute byte blink - enables blinking effect when this bit is set to " 1 ". the blinking is alternated per 32 vertical frames. r1, g1, b1 - these bits are used to specify its relative address character color 1. 2. row control registers, (row 0 - 14) r2, g2, b2 - these bits are used to specify its relative row character color 2. while the corresponding ccs bit is set to 1, color 2 should be chosen. chs - defines double height character to the respective row. cws - defines double width character to the respective row. row # column # 0 1 28 29 30 31 0 1 13 14 display registers row ctrl reg reserved row 15 column# 0 2 3 5 6 8 9 11 12 18 19 26 window1 window2 window3 window4 frame crtl reg pwm d/a crtl reg b7 b6 b5 b4 b3 b2 b1 b0 craddr msb lsb b7 b6 b5 b4 b3 b2 b1 b0 - - - - blink r1 g1 b1 coln 30 b7 b6 b5 b4 b3 b2 b1 b0 - - - r2 g2 b2 chs cws
8/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 3.6 user font ram the user font ram has 288 locations which are allocated between row 0/column 0 and row 7/column 35 to specify 8 user-programmable fonts, as shown in figure 5. each programmable font consists of a 12x18 dot matrix. each row of dot matrix consists of 2 bytes of data which include 4 dummy bits as shown in figure 6. that is, the dot matrix data of each font is stored in 36-byte registers. for example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to col- umn 35, etc. figure 5. user font ram memory map 3.7 character rom the character rom contains 248 built-in characters and symbols from addresses 0 to 247. each char- acter and symbol consists of a 12x18 dot matrix. the detail pattern structures for each character and symbol are shown in 10.0? character and symbol pattern ? on page 15. 3.8 luminance & border generator there are 2 shift registers included in the design which can shift out of luminance and border dots to the color encoder. the bordering and shadowing feature is configured in this block. for bordering effect, the character will be enveloped with blackedge on 4 sides. for shadowing effect, the character is envel- oped with blackedge on right and bottom sides only. 3.9 window and frame control the display frame position is completely controlled by the contents of vertd and hord. the window size and position control are specified in columns 0 to 11 on row 15 of the memory map, as shown in figure 4. window 1 has the highest priority and window 4 has the least, when 2 windows are overlap- ping. more detailed information is described as follows: row # column # 0 1 34 35 36 63 0 1 6 7 user font ram reserved figure 6. data format of font dot matrix nth byte (n+1)th byte 12 bits for 1-row data of font dot matrix dummy bits rightmost dot of font n=even number b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 leftmost dot of font
9/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 1. window control registers: row 15 start(end) addr - these addresses are used to specify the window size. it should be noted that when the start address is greater than the end address, the window will be disa- bled. wen - enables the window display. ccs - when a window is overlapping with the character, character color 2 should be chosen while this bit is set to 1. color 1 is selected otherwise. r, g, b - specifies the color of the relative background window. 2. frame control registers: row 15 vertd - specifies the starting position for vertical display. the total steps are 256, and the increment of each step is 4 horizontal display lines. the initial value is 4 after power-up. hord - defines the starting position for horizontal display. the total steps are 256 and the increment of each step is 6 dots. the initial value is 15 after power-up. ch6-ch0 - defines the character vertical height, which is programmable from 18 to 71 lines. the char- acter vertical height is at least 18 lines if the contents of ch6-ch0 are less than 18. for example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines. if the contents of ch4-ch0 are greater than or equal to 18, it will be regarded as equal to 17. see tables 2 and 3 for a detailed description of this operation. this byte is reserved for internal testing. column 0,3,6,or 9 b7 b6 b5 b4 b3 b2 b1 b0 row start addr msb lsb row end addr msb lsb column 1,4,7,or 10 b7 b6 b5 b4 b3 b2 b1 b0 col start addr msb lsb wen ccs - column 2,5,8,or 11 b7 b6 b5 b4 b3 b2 b1 b0 col end addr msb lsb r g b column 12 b7 b6 b5 b4 b3 b2 b1 b0 vertd msb lsb column 13 b7 b6 b5 b4 b3 b2 b1 b0 hord msb lsb column 14 b7 b6 b5 b4 b3 b2 b1 b0 - ch6 ch5 ch4 ch3 ch2 ch1 ch0 column 15 b7 b6 b5 b4 b3 b2 b1 b0 reserved
10/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology rspace - defines the row to row spacing in each unit of the horizontal line. that is, extra rspace horizontal lines will be appended below each display row, and the maximum space is 31 lines. the initial value is ?0? after power-up. osden - activates the osd operation when this bit is set to "1". the initial value is? 0? after power-up. bsen - enables the bordering and shadowing effect. shadow - activates the shadowing effect if this bit is set, otherwise the bordering is chosen. tric - defines the driving state of output pins rout, gout, bout and fbkg when osd is disabled. that is, while osd is disabled, these 4 pins will drive low if this bit is set to ?1?, otherwise these pins are in high-impedance state. the initial value is ?0? after power-up. blank - forces the fbkg pin output to high while this bit is set to "1". wenclr - clears all wen bits of window control registers when this bit is set to "1". the initial value is ?0? after power-up. ramclr - clears all address bytes of display registers when this bit is set to "1". the initial value is ?0? after power-up. fbkgc - defines the output configuration for fbkg pin. when it is set to "0", the fbkg outputs during the display of characters or windows, otherwise, it outputs only during the display of charac- ters. test - = 0 t normal mode. = 1 t test mode, not allowed in applications. fbkgp - selects the polarity of the output pin fbkg. = 1 t positive polarity fbkg output is selected. = 0 t negative polarity fbkg output is selected . the initial value is ?1? after power-up. pwmck - selects the output options to the htone/pwmck pin. = 0 t ? htone option is selected. = 1 t ? pwmck option is selected with 50/50 duty cycle and is synchronous with the input hflb. the frequency is selected by pwm1, pwm0 as shown in table 4. the initial value is ?0? after power-up. dwe - enables double width. when the bit is set to ?1?, the display of the osd menu can change to half resolution for double character width, and then the number of pixels of each line should be even. hsp - = 1 t accepts positive polarity hsync input. column 16 b7 b6 b5 b4 b3 b2 b1 b0 - - - rspace msb lsb column 17 b7 b6 b5 b4 b3 b2 b1 b0 osden bsen shadow tric blank wenclr ramclr fbkgc column 18 b7 b6 b5 b4 b3 b2 b1 b0 test fbkgp pwmck dwe hsp vsp pwm1 pwm0
11/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology = 0 t accepts negative polarity hsync input. vsp - = 1 t accepts positive polarity vsync input. = 0 t accepts negative polarity vsync input. pwm1, pwm0 - selects the pwmck output frequency. = (0, 0) t xin frequency /8 = (0, 1) t xin frequency /4 = (1, 0) t xin frequency /2 = (1, 1) t xin frequency /1 the initial value is 0, 0 after power-up. notes : when xin is not present, don't write data in any address. if data is written in any address, a malfunction may occur. 3.10 pwm d/a converter there are 8 open-drain pwm d/a outputs (pwm0 to pwm7). the pwm d/a converter output pulse width is programmable by writing data to columns 19-26 registers of row 15 with 8-bit resolution to con- trol the pulse width duration from 0/256 to 255/256. the sampling rate is selected by pwm1, pwm0 as shown in table 4. in applications, all open-drain output pins should be pulled up by external resistors to supply voltage (5v to 9v) for the desired output range. row 15 pwmda0 - pwmda7 - defines the output pulse width of pins pwm0 to pwm7. 3.11 color encoder the decoder generates the video output to rout, gout and bout by integrating window color, bor- der blackedge, luminance output and color selection output (r, g, b) to form the desired video outputs. 4.0 absolute maximum ratings dc supply voltage(vdd,vdda) -0.3 to +7 v ground voltage -0.3 to vdd+0.3 v storage temperature -65 to +150 o c ambient operating temperature 0 to +70 o c table 4. pwmck frequency and pwmda sampling rate (pwm1, pwm0) pwmck freq. pwmda sampling rate ( 0, 0 ) xin frequency /8 xin frequency /(8 * 256) ( 0, 1 ) xin frequency /4 xin frequency /(4 * 256) ( 1, 0 ) xin frequency /2 xin frequency /(2 * 256) ( 1 ,1 ) xin frequency /1 xin frequency /(1 * 256) column 19 | column 26 b7 b6 b5 b4 b3 b2 b1 b0 pwmda0 | pwmda7 msb lsb
12/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 5.0 operating conditions dc supply voltage(vdd,vdda) +4.75 to +5.25 v operating temperature 0 to +70 o c 6.0 electrical characteristics (under operating conditions) 7.0 switching characteristic (under operating conditions) symbol parameter conditions(notes) min. max. unit v ih input high voltage - 0.7 * vdd vdd+0.3 v v il input low voltage - vss-0.3 0.3 * vdd ( 0.2 * vdd for ssb pin ) v v oh output high volt- age i oh 3 -24 ma vdd-0.8 - v v ol output low volt- age i ol 24 ma - 0.5 v v odh open drain out- put high voltage - (for all od pins, pulled up by external 5 to 9v power supply) 5 9 v v odl open drain out- put low voltage 5 ma 3 i dol ( for all od pins ) - 0.5 v i sb standby current vin = vdd, i load = 0ua l - 12 ma i cc operating current pixel rate=96mhz i load = 0ua - 20 ma symbol parameter min. typ. max. unit f hflb hflb input frequency 15 - 120 khz t r output rise time - - 5 ns t f output fall time - - 5 ns t bcsu ssb to sck set-up time 200 - - ns t bch ssb to sck hold time 100 - - ns t dcsu sda to sck set-up time 200 - - ns t dch sda to sck hold time 100 - - ns t sckh sck high time 500 - - ns t sckl sck low time 500 - - ns t su:sta start condition set-up time 500 - - ns t hd:sta start condition hold time 500 - - ns t su:sto stop condition set-up time 500 - - ns
13/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 8.0 timing diagrams t hd:sto stop condition hold time 500 - - ns t setup hflb delay to rising edge of pixel clock 2 6 ns t hold minimum pulse width of hflb 25 ns t pd propagation delay of output to pixel clock 10 ns pixin pixel clock input 6 96 mhz symbol parameter min. typ. max. unit figure 7. data interface timing (spi) sck ssb sda t sckl t sckh t bcsu t dcsu t dch t bch figure 8. data interface timing (i 2 c) sck sda t su:sta t sckh t hd:sta t sckl t dcsu t dch t su:sto t hd:sto plxin r,g,b, fbkg htone t pd t pd:: propagation delay to r,g,b, fbkg and htone outputs setup t hold t hflb figure 9. output and hflb timing to pixel clock
14/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 9.0 package dimension 9.1 16 pdip 300mil unit:mil 9.2 24 pdip 300mil unit: mil 75 +/-20 90 +/-20 250 +/-4 55 +/-20 90 +/-20 312 +/-12 65 +/-4 55 +/-4 310max 350 +/-20 10 r10max (4x ) 100ty p 18 +/- 2typ 60 +/- 5typ 115 min 750 +/-10 15 min 35 +/-5 7 typ r40 15 max 930+/-10 r40 55+/-20 312+/-12 r10max (4x) 80+/-20 250+/-4 350+/-20 10 18+/- 2typ 60+/- 5typ 15min. 15max 115min 100ty p 35+/-5 7ty p 1245+/-10 65+/-4 65+/-4
15/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 9.3 16-pin sop 300mil unit: mil 9.4 24-pin sop 300mil 10.0 character and symbol pattern please see the attachment. 0.015x45 o 7 o (4x) 0.028 +0.022 /-0.013 0.295 +/-0.004 0.406 +/-0.013 0.406 +/-0.008 0.016 +/-0.004 0.050 0.098 +/-0.006 0.091 (4x) 0.45mm +/-0.1 15.0mm /+0.4 -0.1 1.27mm 12 1 24 13 5.3mm +0.3/-0.1 7.9mm+/-0.4 6.9mm 0.2mm +0.1/-0.05 0.5mm+/-0.2 0.1mm +0.2/-0.05 1.85mm/+0.4 -0.15 myson technology usa, inc. http://www.myson.com 20111 stevens creek blvd. #138 cupertino, ca. 95014, u.s.a. tel: 408-252-8788 fax: 408-252-8789 sales@myson.com myson technology, inc. http://www.myson.com.tw no. 2, industry e. rd. iii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5784866 fax: 886-3-5785002
this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sales o f the product. 1/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology features general description block diagram ? horizontal sync input may be up to 120 khz. ? acceptable wide-range pixel clock up to 96mhz from xin pin. ? full-screen display consists of 15 (rows) by 30 (col- umns) characters. ? 12 x 18 dot matrix per character. ? total of 256 characters and graphic fonts including 248 mask rom fonts and 8 programmable ram fonts. ? 8 color selection maximum per display character. ? double character height and/or width control. ? programmable positioning for display screen cen- ter. ? bordering, shadowing and blinking effect. ? programmable vertical character height (18 to 71 lines) control. ? row to row spacing register to manipulate the con- stant display height. ? 4 programmable background windows with multi- level operation. ? software clears for display frame. ? half tone and fast blanking output. ? 8-channel/8-bit pwm d/a converter output. ? compatible with spi bus or i 2 c interface with address 7ah (slave address is mask option). ? 16 or 24-pin pdip/sop package. on-screen-display for lcd monitor MTV118 is designed for lcd monitor appli- cations to display the built-in characters or fonts onto an lcd monitor screen. the display oper- ates by transferring data and control information from the micro controller to the ram through a serial data interface. it can execute full screen displays automatically and specific functions such as character bordering, shadowing, blinking, dou- ble height and width, font by font color control, frame positioning, frame size control by character height and windowing effect. moreover, MTV118 also provides 8 pwm dac channels with 8-bit resolution and a pwm clock output for external digital-to-analog control. serial data interface address bus administrator vertical display control display & row control registers color encoder windows & frame control wr wg wb fbkgc blank lumar lumag lumab blink vclkx data vertd hord ch 8 8 7 bsen shadow osdenb hsp vsp horizontal display control clock generator 8 data lpn cws vclks 5 data cws chs 8 lumar lumag lumab blink craddr 8 luma border arwdb hdren vclkx hord 8 ch chs vertd 7 8 lpn nrow vdren 5 rcaddr daddr fontaddr winaddr pwmaddr 5 9 9 5 5 arwdb hdren vdren nrow data row, col ack 8 9 character rom user font ram luminance & bordger generator vdd vss vdda vssa rout gout bout fbkg htone hflb nc xin vflb ssb sck sda vsp hsp pwm d/a converter pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 8 data 8 power on reset prb
2/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 1.0 pin connection 2.0 pin descriptions name i/o pin # descriptions n16 n24 vss - 1 1 ground. this ground pin is used for internal circuitry. xin i 2 2 pixel clock input. this is a clock input pin. MTV118 is driven by an external pixel clock source for all the logics inside. the fre- quency of xin must be the integral time of pin hflb. nc i 3 3 no connection. vdd - 4 4 power supply. positive 5 v dc supply for internal circuitry. a 0.1uf decoupling capacitor should be connected across vdd and vss. hflb i 5 5 horizontal input. this pin is used to input the horizontal synchro- nizing signal. it is a leading edge trigger and has an internal pull- up resistor. ssb i 6 6 serial interface enabler. it is used to enable the serial data and is also used to select the operation of i 2 c or spi bus. if this pin is left floating, i 2 c bus is enabled, otherwise the spi bus is enabled. sda i 7 7 serial data input. the external data transfers through this pin to internal display registers and control registers. it has an internal pull-up resistor. sck i 8 8 serial clock input. the clock-input pin is used to synchronize the data transfer. it has an internal pull-up resistor. pwm0 o - 9 open-drain pwm d/a converter 0. the output pulse width is programmable by the register of row 15, column 19. pwm1 o - 10 open-drain pwm d/a converter 1. the output pulse width is programmable by the register of row 15, column 20. pwm2 o - 11 open-drain pwm d/a converter 2. the output pulse width is programmable by the register of row 15, column 21. vss xin nc vdd hflb ssb sda sck vss rout gout bout fbkg htone/pwmck vflb vdd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MTV118 vss xin nc vdd hflb ssb sda sck pwm0 pwm1 pwm2 pwm3 vss rout gout bout fbkg htone/pwmck vflb vdd pwm7 pwm6 pwm5 pwm4 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 MTV118n24
3/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 3.0 functional descriptions 3.1 serial data interface the serial data interface receives data transmitted from an external controller. there are 2 types of bus which can be accessed through the serial data interface: spi bus and i 2 c bus. 3.1.1 spi bus when the ssb pin is pulled to a high or low level, the spi bus operation is selected. a valid trans- mission should start from pulling ssb to low level, enabling the MTV118 receiving mode and retaining the low level until the last cycle for a complete data packet transfer. the protocol is shown in figure1 on page4. there are 3 transmission formats as shown below: format (a) r - c - d ? r - c - d ? r - c - d format (b) r - c - d ? c - d ? c - d ? c - d format (c) r - c - d ? d ? d ? d ? d ? d r=row address, c=column address, d=display data pwm3 o - 12 open-drain pwm d/a converter 3. the output pulse width is programmable by the register of row 15, column 22. pwm4 o - 13 open-drain pwm d/a converter 4. the output pulse width is programmable by the register of row 15, column 23. pwm5 o - 14 open-drain pwm d/a converter 5. the output pulse width is programmable by the register of row 15, column 24. pwm6 o - 15 open-drain pwm d/a converter 6. the output pulse width is programmable by the register of row 15, column 25. pwm7 o - 16 open-drain pwm d/a converter 7. the output pulse width is programmable by the register of row 15, column 26. vdd - 9 17 power supply. positive 5 v dc supply for internal circuitry and a 0.1uf decoupling capacitor should be connected across vdd and vss. vflb i 10 18 vertical input. this pin is used to input the vertical synchronizing signal. it is triggered by lead and has an internal pull-up resistor. htone / pwmck o 11 19 half tone output / pwm clock output. this is a multiplexed pin selected by the pwmck bit. this pin can be a pwm clock or used to attenuate r, g, b gain of vga for the transparent windowing effect. fbkg o 12 20 fast blanking output. it is used to cut off external r, g, b sig- nals of vga while this chip is displaying characters or windows. bout o 13 21 blue color output. this is a blue color video signal output. gout o 14 22 green color output. this is a green color video signal output. rout o 15 23 red color output. this is a red color video signal output. vss - 16 24 ground. this ground pin is used for internal circuitry. name i/o pin # descriptions n16 n24
4/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 3.1.2 i 2 c bus i 2 c bus operation is only selected when the ssb pin is left floating. a valid transmission should begin from writing the slave address 7ah, which is mask option, to MTV118. the protocol is shown in figure 2 on page 4.. there are 3 transmission formats as shown below: format (a) s - r - c - d ? r - c - d ? r - c - d format (b) s - r - c - d ? c - d ? c - d ? c - d format (c) s - r - c - d ? d ? d ? d ? d ? d s=slave address, r=row address, c=column address, d=display data each arbitrary length of data packet consists of 3 portions: row address (r), column address (c) and display data (d). format (a) is suitable for updating small amounts of data which will be allocated with different row and column addresses. format (b) is recommended for updating data that has the same row address but a different column address. massive data updating or full screen data changes should be done in format (c) to increase transmission efficiency. the row and column addresses will be incre- mented automatically when format (c) is applied. furthermore, the undefined locations in display or font ram should be filled with dummy data. there are 3 types of data which should be accessed through the serial data interface: address bytes of display registers, attribute bytes of display registers and user font ram data. the protocol is the same for all except bits 5 and 6 of the row addresses. the msb(b7) is used to distinguish row and column addresses when transferring data from an external controller. bit 6 of the row address is used to distin- guish display registers and user font ram data and bit6 of the column address is used to differentiate the column address for formats (a), (b) and (c), respectively. bit 5 of the row address for display regis- ters is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to "1". the configuration of transmission formats is shown in table1 on page5. ms b lsb ssb sck sda first byte last byte figure 1. data transmission protocol (spi) figure 2. data transmission protocol (i 2 c) sck sda first byte ?@?@?@?@ ?@ start ack second byte last byte ack stop b7 b6 b0 b7 b0
5/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology the data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). the alternation between transmission for- mats is configured as the state diagram shown in figure3 on page5. 3.2 address bus administrator the administrator manages bus address arbitration of internal registers or user font ram during exter- nal data write-in. the external data write through serial data interface to registers must be synchronized by internal display timing. in addition, the administrator also provides automatic incrementation to the address bus when external writing occurs using format (c). 3.3 vertical display control the vertical display control can generate different vertical display sizes for most display standards in current monitors. the vertical display size is calculated with the information of a double character height bit(chs) and a vertical display height control register(ch6-ch0).the algorithms of a repeating charac- ter line display are shown in tables 2 and 3. the programmable vertical size range is 270 lines to max- imum 2130 lines. table 1. configuration of transmission formats address b7 b6 b5 b4 b3 b2 b1 b0 format address bytes of display reg. row 1 0 0 x r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b column c 0 1 x c4 c3 c2 c1 c0 c attribute bytes of display reg. row 1 0 1 x r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b column c 0 1 x c4 c3 c2 c1 c0 c user fonts ram row 1 1 x x x r2 r1 r0 a,b,c column ab 0 0 c5 c4 c3 c2 c1 c0 a,b column c 0 1 c5 c4 c3 c2 c1 c0 c initiate row col c col ab da c da ab 1, x 0, 1 0, 0 x, x x, x 0, 1 1, x 1, x format (a) format (b) format (c) x, x 0, x input = b7, b6 0, 0 figure 3. transmission state diagram
6/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology the vertical display center for a full-screen display may be figured out according to the information of the vertical starting position register (vertd) and vflb input. the vertical delay starting from the lead- ing edge of vflb is calculated using the following equation: vertical delay time = ( vertd * 4 + 1 ) * h where h = 1 horizontal line display time note: ?v? means the nth line in the character would be repeated once, while ?-? means the nth line in the character would not be repeated. 3.4 horizontal display control the horizontal display control is used to generate control timing for a horizontal display based on dou- ble character width bit (cws), horizontal positioning register (hord) and hflb input. a horizontal dis- play line includes 360 dots for 30 display characters and the remaining dots for a blank region. the horizontal delay starting from the hflb leading edge is calculated using the following equation: horizontal delay time = ( hord * 6 + 49) * p where p = 1 xin pixel display time 3.5 display & row control registers the internal ram contains display and row control registers. the display registers have 450 locations which are allocated between row 0/column 0 and row 14/column 29 as shown in figure 4. each display register has its corresponding character address on the address byte, and 1 blink bit and its corre- sponding color bits on attribute bytes. the row control register is allocated at column 30 for row 0 to row 14; it is used to set character size for each respective row. if the double width character (cws) is cho- table 2. repeat line weight of character ch6-ch0 repeat line weight ch6,ch5=11 +18*3 ch6,ch5=10 +18*2 ch6,ch5=0x +18 ch4=1 +16 ch3=1 +8 ch2=1 +4 ch1=1 +2 ch0=1 +1 table 3. repeat line number of character repeater line weight repeat line # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 - - - - - - - - v - - - - - - - - - +2 - - - - v - - - - - - - v - - - - - +4 - - v - - - v - - - v - - - v - - - +8 - v - v - v - v - v - v - v - v - - +16 - v v v v v v v v v v v v v v v v - +17 v v v v v v v v v v v v v v v v v - +18 v v v v v v v v v v v v v v v v v v
7/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology sen, only even column characters may be displayed on-screen and the odd column characters will be hidden. figure 4. memory map 3.5.1 register descriptions 1. (i) display register, (row 0 - 14, column 0 - 29) address byte craddr - defines rom character and user-programmable fonts address. (a) 0 ~ 247 t 248 built-in characters and graphic symbols (b) 248 ~ 255 t 8 user-programmable fonts attribute byte blink - enables blinking effect when this bit is set to " 1 ". the blinking is alternated per 32 vertical frames. r1, g1, b1 - these bits are used to specify its relative address character color 1. 2. row control registers, (row 0 - 14) r2, g2, b2 - these bits are used to specify its relative row character color 2. while the corresponding ccs bit is set to 1, color 2 should be chosen. chs - defines double height character to the respective row. cws - defines double width character to the respective row. row # column # 0 1 28 29 30 31 0 1 13 14 display registers row ctrl reg reserved row 15 column# 0 2 3 5 6 8 9 11 12 18 19 26 window1 window2 window3 window4 frame crtl reg pwm d/a crtl reg b7 b6 b5 b4 b3 b2 b1 b0 craddr msb lsb b7 b6 b5 b4 b3 b2 b1 b0 - - - - blink r1 g1 b1 coln 30 b7 b6 b5 b4 b3 b2 b1 b0 - - - r2 g2 b2 chs cws
8/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 3.6 user font ram the user font ram has 288 locations which are allocated between row 0/column 0 and row 7/column 35 to specify 8 user-programmable fonts, as shown in figure 5. each programmable font consists of a 12x18 dot matrix. each row of dot matrix consists of 2 bytes of data which include 4 dummy bits as shown in figure 6. that is, the dot matrix data of each font is stored in 36-byte registers. for example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to col- umn 35, etc. figure 5. user font ram memory map 3.7 character rom the character rom contains 248 built-in characters and symbols from addresses 0 to 247. each char- acter and symbol consists of a 12x18 dot matrix. the detail pattern structures for each character and symbol are shown in 10.0? character and symbol pattern ? on page 15. 3.8 luminance & border generator there are 2 shift registers included in the design which can shift out of luminance and border dots to the color encoder. the bordering and shadowing feature is configured in this block. for bordering effect, the character will be enveloped with blackedge on 4 sides. for shadowing effect, the character is envel- oped with blackedge on right and bottom sides only. 3.9 window and frame control the display frame position is completely controlled by the contents of vertd and hord. the window size and position control are specified in columns 0 to 11 on row 15 of the memory map, as shown in figure 4. window 1 has the highest priority and window 4 has the least, when 2 windows are overlap- ping. more detailed information is described as follows: row # column # 0 1 34 35 36 63 0 1 6 7 user font ram reserved figure 6. data format of font dot matrix nth byte (n+1)th byte 12 bits for 1-row data of font dot matrix dummy bits rightmost dot of font n=even number b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 leftmost dot of font
9/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 1. window control registers: row 15 start(end) addr - these addresses are used to specify the window size. it should be noted that when the start address is greater than the end address, the window will be disa- bled. wen - enables the window display. ccs - when a window is overlapping with the character, character color 2 should be chosen while this bit is set to 1. color 1 is selected otherwise. r, g, b - specifies the color of the relative background window. 2. frame control registers: row 15 vertd - specifies the starting position for vertical display. the total steps are 256, and the increment of each step is 4 horizontal display lines. the initial value is 4 after power-up. hord - defines the starting position for horizontal display. the total steps are 256 and the increment of each step is 6 dots. the initial value is 15 after power-up. ch6-ch0 - defines the character vertical height, which is programmable from 18 to 71 lines. the char- acter vertical height is at least 18 lines if the contents of ch6-ch0 are less than 18. for example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines. if the contents of ch4-ch0 are greater than or equal to 18, it will be regarded as equal to 17. see tables 2 and 3 for a detailed description of this operation. this byte is reserved for internal testing. column 0,3,6,or 9 b7 b6 b5 b4 b3 b2 b1 b0 row start addr msb lsb row end addr msb lsb column 1,4,7,or 10 b7 b6 b5 b4 b3 b2 b1 b0 col start addr msb lsb wen ccs - column 2,5,8,or 11 b7 b6 b5 b4 b3 b2 b1 b0 col end addr msb lsb r g b column 12 b7 b6 b5 b4 b3 b2 b1 b0 vertd msb lsb column 13 b7 b6 b5 b4 b3 b2 b1 b0 hord msb lsb column 14 b7 b6 b5 b4 b3 b2 b1 b0 - ch6 ch5 ch4 ch3 ch2 ch1 ch0 column 15 b7 b6 b5 b4 b3 b2 b1 b0 reserved
10/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology rspace - defines the row to row spacing in each unit of the horizontal line. that is, extra rspace horizontal lines will be appended below each display row, and the maximum space is 31 lines. the initial value is ?0? after power-up. osden - activates the osd operation when this bit is set to "1". the initial value is? 0? after power-up. bsen - enables the bordering and shadowing effect. shadow - activates the shadowing effect if this bit is set, otherwise the bordering is chosen. tric - defines the driving state of output pins rout, gout, bout and fbkg when osd is disabled. that is, while osd is disabled, these 4 pins will drive low if this bit is set to ?1?, otherwise these pins are in high-impedance state. the initial value is ?0? after power-up. blank - forces the fbkg pin output to high while this bit is set to "1". wenclr - clears all wen bits of window control registers when this bit is set to "1". the initial value is ?0? after power-up. ramclr - clears all address bytes of display registers when this bit is set to "1". the initial value is ?0? after power-up. fbkgc - defines the output configuration for fbkg pin. when it is set to "0", the fbkg outputs during the display of characters or windows, otherwise, it outputs only during the display of charac- ters. test - = 0 t normal mode. = 1 t test mode, not allowed in applications. fbkgp - selects the polarity of the output pin fbkg. = 1 t positive polarity fbkg output is selected. = 0 t negative polarity fbkg output is selected . the initial value is ?1? after power-up. pwmck - selects the output options to the htone/pwmck pin. = 0 t ? htone option is selected. = 1 t ? pwmck option is selected with 50/50 duty cycle and is synchronous with the input hflb. the frequency is selected by pwm1, pwm0 as shown in table 4. the initial value is ?0? after power-up. dwe - enables double width. when the bit is set to ?1?, the display of the osd menu can change to half resolution for double character width, and then the number of pixels of each line should be even. hsp - = 1 t accepts positive polarity hsync input. column 16 b7 b6 b5 b4 b3 b2 b1 b0 - - - rspace msb lsb column 17 b7 b6 b5 b4 b3 b2 b1 b0 osden bsen shadow tric blank wenclr ramclr fbkgc column 18 b7 b6 b5 b4 b3 b2 b1 b0 test fbkgp pwmck dwe hsp vsp pwm1 pwm0
11/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology = 0 t accepts negative polarity hsync input. vsp - = 1 t accepts positive polarity vsync input. = 0 t accepts negative polarity vsync input. pwm1, pwm0 - selects the pwmck output frequency. = (0, 0) t xin frequency /8 = (0, 1) t xin frequency /4 = (1, 0) t xin frequency /2 = (1, 1) t xin frequency /1 the initial value is 0, 0 after power-up. notes : when xin is not present, don't write data in any address. if data is written in any address, a malfunction may occur. 3.10 pwm d/a converter there are 8 open-drain pwm d/a outputs (pwm0 to pwm7). the pwm d/a converter output pulse width is programmable by writing data to columns 19-26 registers of row 15 with 8-bit resolution to con- trol the pulse width duration from 0/256 to 255/256. the sampling rate is selected by pwm1, pwm0 as shown in table 4. in applications, all open-drain output pins should be pulled up by external resistors to supply voltage (5v to 9v) for the desired output range. row 15 pwmda0 - pwmda7 - defines the output pulse width of pins pwm0 to pwm7. 3.11 color encoder the decoder generates the video output to rout, gout and bout by integrating window color, bor- der blackedge, luminance output and color selection output (r, g, b) to form the desired video outputs. 4.0 absolute maximum ratings dc supply voltage(vdd,vdda) -0.3 to +7 v ground voltage -0.3 to vdd+0.3 v storage temperature -65 to +150 o c ambient operating temperature 0 to +70 o c table 4. pwmck frequency and pwmda sampling rate (pwm1, pwm0) pwmck freq. pwmda sampling rate ( 0, 0 ) xin frequency /8 xin frequency /(8 * 256) ( 0, 1 ) xin frequency /4 xin frequency /(4 * 256) ( 1, 0 ) xin frequency /2 xin frequency /(2 * 256) ( 1 ,1 ) xin frequency /1 xin frequency /(1 * 256) column 19 | column 26 b7 b6 b5 b4 b3 b2 b1 b0 pwmda0 | pwmda7 msb lsb
12/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 5.0 operating conditions dc supply voltage(vdd,vdda) +4.75 to +5.25 v operating temperature 0 to +70 o c 6.0 electrical characteristics (under operating conditions) 7.0 switching characteristic (under operating conditions) symbol parameter conditions(notes) min. max. unit v ih input high voltage - 0.7 * vdd vdd+0.3 v v il input low voltage - vss-0.3 0.3 * vdd ( 0.2 * vdd for ssb pin ) v v oh output high volt- age i oh 3 -24 ma vdd-0.8 - v v ol output low volt- age i ol 24 ma - 0.5 v v odh open drain out- put high voltage - (for all od pins, pulled up by external 5 to 9v power supply) 5 9 v v odl open drain out- put low voltage 5 ma 3 i dol ( for all od pins ) - 0.5 v i sb standby current vin = vdd, i load = 0ua l - 12 ma i cc operating current pixel rate=96mhz i load = 0ua - 20 ma symbol parameter min. typ. max. unit f hflb hflb input frequency 15 - 120 khz t r output rise time - - 5 ns t f output fall time - - 5 ns t bcsu ssb to sck set-up time 200 - - ns t bch ssb to sck hold time 100 - - ns t dcsu sda to sck set-up time 200 - - ns t dch sda to sck hold time 100 - - ns t sckh sck high time 500 - - ns t sckl sck low time 500 - - ns t su:sta start condition set-up time 500 - - ns t hd:sta start condition hold time 500 - - ns t su:sto stop condition set-up time 500 - - ns
13/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 8.0 timing diagrams t hd:sto stop condition hold time 500 - - ns t setup hflb delay to rising edge of pixel clock 2 6 ns t hold minimum pulse width of hflb 25 ns t pd propagation delay of output to pixel clock 10 ns pixin pixel clock input 6 96 mhz symbol parameter min. typ. max. unit figure 7. data interface timing (spi) sck ssb sda t sckl t sckh t bcsu t dcsu t dch t bch figure 8. data interface timing (i 2 c) sck sda t su:sta t sckh t hd:sta t sckl t dcsu t dch t su:sto t hd:sto plxin r,g,b, fbkg htone t pd t pd:: propagation delay to r,g,b, fbkg and htone outputs setup t hold t hflb figure 9. output and hflb timing to pixel clock
14/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 9.0 package dimension 9.1 16 pdip 300mil unit:mil 9.2 24 pdip 300mil unit: mil 75 +/-20 90 +/-20 250 +/-4 55 +/-20 90 +/-20 312 +/-12 65 +/-4 55 +/-4 310max 350 +/-20 10 r10max (4x ) 100ty p 18 +/- 2typ 60 +/- 5typ 115 min 750 +/-10 15 min 35 +/-5 7 typ r40 15 max 930+/-10 r40 55+/-20 312+/-12 r10max (4x) 80+/-20 250+/-4 350+/-20 10 18+/- 2typ 60+/- 5typ 15min. 15max 115min 100ty p 35+/-5 7ty p 1245+/-10 65+/-4 65+/-4
15/15 MTV118 revision 2.0 01/01/1999 MTV118 myson technology 9.3 16-pin sop 300mil unit: mil 9.4 24-pin sop 300mil 10.0 character and symbol pattern please see the attachment. 0.015x45 o 7 o (4x) 0.028 +0.022 /-0.013 0.295 +/-0.004 0.406 +/-0.013 0.406 +/-0.008 0.016 +/-0.004 0.050 0.098 +/-0.006 0.091 (4x) 0.45mm +/-0.1 15.0mm /+0.4 -0.1 1.27mm 12 1 24 13 5.3mm +0.3/-0.1 7.9mm+/-0.4 6.9mm 0.2mm +0.1/-0.05 0.5mm+/-0.2 0.1mm +0.2/-0.05 1.85mm/+0.4 -0.15 myson technology usa, inc. http://www.myson.com 20111 stevens creek blvd. #138 cupertino, ca. 95014, u.s.a. tel: 408-252-8788 fax: 408-252-8789 sales@myson.com myson technology, inc. http://www.myson.com.tw no. 2, industry e. rd. iii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5784866 fax: 886-3-5785002

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